XPS: CLCCA: ENHANCING THE PROGRAMMABILITY OF HETEROGENEOUS MANYCORE SYSTEMS

  • Bhattacharjee, Abhishek, (PI)

Project Details

Description

As computing devices are used to solve increasingly complex and diverse problems with ever-increasing multidimensional data-sets, programmers are tasked with writing high-performance and energy-efficient code. To run this code, processor vendors are adopting heterogeneous systems, where conventional general-purpose cores are integrated with accelerators like graphics processing units (GPUs), cryptographic accelerators, database accelerators, and video encoders/decoders. To ensure the widespread adoption of these systems, it is essential that their programming models are effective and easy to use. Unfortunately, current programming models for these systems are challenging, requiring the programmer to explicitly allocate, manage, and marshal memory back and forth between cores and accelerators. As a result, software is often error-prone and buggy, and suffers overheads from data replication and movement. As future systems incorporate increasing levels of heterogeneity, this problem will worsen.This proposal develops unified address spaces for cores and accelerators, which is a key part of an effective programming model. A unified address space (in both virtual and physical addresses) increases system programmability because: (1) programmers need not manually allocate and manage their data movement between hundreds of heterogeneous compute units; (2) the system automatically allocates, replicates, and migrates data among heterogeneous components as execution shifts; (3) these systems support new algorithms that require simultaneous core and accelerator access to common data structures (e.g., producer-consumer programs where CPUs and GPUs communicate through software task queues); (4) programs are now more portable across systems with alternate memory hierarchies. This work studies mechanisms to support these benefits (while maintaining high performance and low power) by developing novel hardware (e.g., new memory controllers, Translation Lookaside Buffer augmentations, shootdown mechanisms) and operating system (OS) support (e.g., new OS memory allocation mechanisms and support for page allocation, replication, and migration on heterogeneous systems and memory).
StatusFinished
Effective start/end date9/1/138/31/16

Funding

  • National Science Foundation (National Science Foundation (NSF))

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