1000-V 9.1-mΩ · cm2 normally off 4H-SiC lateral RESURF JFET for power integrated circuit applications

Yongxi Zhang; Kuang Sheng; Ming Su; Jian H. Zhao; Petre Alexandrov; Leonid Fursin

doi:10.1109/LED.2007.895448

1000-V 9.1-mΩ · cm² normally off 4H-SiC lateral RESURF JFET for power integrated circuit applications

Yongxi Zhang, Kuang Sheng, Ming Su, Jian H. Zhao, Petre Alexandrov, Leonid Fursin

School of Engineering, Electrical & Computer Engineering

Research output: Contribution to journal › Article › peer-review

29 Scopus citations

Abstract

A 4H-SiC normally off vertical channel lateral reduced-surface electric-field (RESURF) junction field-effect transistor (JFET) with a blocking voltage V_br of 1028 V and a specific on-resistance R_on-sp of 9.1 mΩ · cm² has been experimentally demonstrated. The device has a V_br²/R_on-sp figure-of-merit of 116 MW/cm², which is the highest value achieved to date on a 4H-SiC lateral power transistor. Also reported is a larger JFET that is capable of handling over 0.5-A current on an active area of 4.01 × 10^-3 cm². The fabricated double-RESURF devices have a vertical channel length of 1.8 μm, created by tilted aluminum (Al) implantation on the sidewalls of deep trenches, and a lateral drift-region length of 7.5 μm. In addition, low-voltage logic-inverter circuits based on the same lateral JFET process have been monolithically integrated on the same chip. Proper logic-inverter function has also been demonstrated.

Original language	English (US)
Pages (from-to)	404-407
Number of pages	4
Journal	IEEE Electron Device Letters
Volume	28
Issue number	5
DOIs	https://doi.org/10.1109/LED.2007.895448
State	Published - May 2007

All Science Journal Classification (ASJC) codes

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

Keywords

Junction field-effect transistor (JFET)
Normally off
Power integrated circuits
Reduced-surface electric-field (RESURF) effect
Silicon carbide (SiC)

Access to Document

10.1109/LED.2007.895448

Cite this

@article{769885b9765543d39a1382fd56e0ba83,

title = "1000-V 9.1-mΩ · cm2 normally off 4H-SiC lateral RESURF JFET for power integrated circuit applications",

abstract = "A 4H-SiC normally off vertical channel lateral reduced-surface electric-field (RESURF) junction field-effect transistor (JFET) with a blocking voltage Vbr of 1028 V and a specific on-resistance Ron-sp of 9.1 mΩ · cm2 has been experimentally demonstrated. The device has a Vbr2/Ron-sp figure-of-merit of 116 MW/cm2, which is the highest value achieved to date on a 4H-SiC lateral power transistor. Also reported is a larger JFET that is capable of handling over 0.5-A current on an active area of 4.01 × 10-3 cm2. The fabricated double-RESURF devices have a vertical channel length of 1.8 μm, created by tilted aluminum (Al) implantation on the sidewalls of deep trenches, and a lateral drift-region length of 7.5 μm. In addition, low-voltage logic-inverter circuits based on the same lateral JFET process have been monolithically integrated on the same chip. Proper logic-inverter function has also been demonstrated.",

keywords = "Junction field-effect transistor (JFET), Normally off, Power integrated circuits, Reduced-surface electric-field (RESURF) effect, Silicon carbide (SiC)",

author = "Yongxi Zhang and Kuang Sheng and Ming Su and Zhao, {Jian H.} and Petre Alexandrov and Leonid Fursin",

note = "Funding Information: Manuscript received February 15, 2007. This work was sponsored by the DARPA/MTO Robust Integrated Power Electronics (RIPE) Program under Air Force Contract FA8650-05-C-7204. The review of this letter was arranged by Editor S.-H. Ryu. Y. Zhang, K. Sheng, M. Su, and J. H. Zhao are with SiCLAB, Department of Electrical and Computer Engineering, Rutgers University, Piscataway, NJ 08854 USA (e-mail: jzhao@ece.rutgers.edu). P. Alexandrov and L. Fursin are with United Silicon Carbide, Inc., New Brunswick Tech Center, New Brunswick, NJ 08901 USA. Color versions of one or more of the figures in this letter are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/LED.2007.895448",

year = "2007",

month = may,

doi = "10.1109/LED.2007.895448",

language = "English (US)",

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journal = "IEEE Electron Device Letters",

issn = "0741-3106",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

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T1 - 1000-V 9.1-mΩ · cm2 normally off 4H-SiC lateral RESURF JFET for power integrated circuit applications

AU - Zhang, Yongxi

AU - Sheng, Kuang

AU - Su, Ming

AU - Zhao, Jian H.

AU - Alexandrov, Petre

AU - Fursin, Leonid

N1 - Funding Information: Manuscript received February 15, 2007. This work was sponsored by the DARPA/MTO Robust Integrated Power Electronics (RIPE) Program under Air Force Contract FA8650-05-C-7204. The review of this letter was arranged by Editor S.-H. Ryu. Y. Zhang, K. Sheng, M. Su, and J. H. Zhao are with SiCLAB, Department of Electrical and Computer Engineering, Rutgers University, Piscataway, NJ 08854 USA (e-mail: jzhao@ece.rutgers.edu). P. Alexandrov and L. Fursin are with United Silicon Carbide, Inc., New Brunswick Tech Center, New Brunswick, NJ 08901 USA. Color versions of one or more of the figures in this letter are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/LED.2007.895448

PY - 2007/5

Y1 - 2007/5

N2 - A 4H-SiC normally off vertical channel lateral reduced-surface electric-field (RESURF) junction field-effect transistor (JFET) with a blocking voltage Vbr of 1028 V and a specific on-resistance Ron-sp of 9.1 mΩ · cm2 has been experimentally demonstrated. The device has a Vbr2/Ron-sp figure-of-merit of 116 MW/cm2, which is the highest value achieved to date on a 4H-SiC lateral power transistor. Also reported is a larger JFET that is capable of handling over 0.5-A current on an active area of 4.01 × 10-3 cm2. The fabricated double-RESURF devices have a vertical channel length of 1.8 μm, created by tilted aluminum (Al) implantation on the sidewalls of deep trenches, and a lateral drift-region length of 7.5 μm. In addition, low-voltage logic-inverter circuits based on the same lateral JFET process have been monolithically integrated on the same chip. Proper logic-inverter function has also been demonstrated.

AB - A 4H-SiC normally off vertical channel lateral reduced-surface electric-field (RESURF) junction field-effect transistor (JFET) with a blocking voltage Vbr of 1028 V and a specific on-resistance Ron-sp of 9.1 mΩ · cm2 has been experimentally demonstrated. The device has a Vbr2/Ron-sp figure-of-merit of 116 MW/cm2, which is the highest value achieved to date on a 4H-SiC lateral power transistor. Also reported is a larger JFET that is capable of handling over 0.5-A current on an active area of 4.01 × 10-3 cm2. The fabricated double-RESURF devices have a vertical channel length of 1.8 μm, created by tilted aluminum (Al) implantation on the sidewalls of deep trenches, and a lateral drift-region length of 7.5 μm. In addition, low-voltage logic-inverter circuits based on the same lateral JFET process have been monolithically integrated on the same chip. Proper logic-inverter function has also been demonstrated.

KW - Junction field-effect transistor (JFET)

KW - Normally off

KW - Power integrated circuits

KW - Reduced-surface electric-field (RESURF) effect

KW - Silicon carbide (SiC)

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JO - IEEE Electron Device Letters

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