A fully integrated quartz MEMS VHF TCXO

R. L. Kubena, F. P. Stratton, H. D. Nguyen, D. J. Kirby, D. T. Chang, R. J. Joyce, Y. K. Yong, J. F. Garstecki, M. D. Cross, S. E. Seman

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Scopus citations

Abstract

We report on a 32-MHz quartz TCXO fully integrated with commercial CMOS electronics and vacuum packaged at wafer level using a low-temperature MEMS-after quartz process. The novel quartz resonator design provides for stress isolation from the CMOS substrate thereby yielding classical AT-cut f/T profiles and low hysteresis which can be compensated to < ± 0.2 ppm over temperature using on-chip third-order compensation circuity. The TCXO operates at low power of 2.5 mW and can be thinned to ≤ 300 μm as part of the wafer-level eutectic encapsulation. Full integration with large SOA CMOS wafers is possible using carrier wafer techniques.

Original languageEnglish (US)
Title of host publication2017 Joint Conference of the European Frequency and Time Forum and IEEE International Frequency Control Symposium, EFTF/IFC 2017 - Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages68-71
Number of pages4
ISBN (Electronic)9781538629161
DOIs
StatePublished - Oct 27 2017
Event2017 Joint Conference of the European Frequency and Time Forum and IEEE International Frequency Control Symposium, EFTF/IFC 2017 - Besancon, France
Duration: Jul 9 2017Jul 13 2017

Publication series

Name2017 Joint Conference of the European Frequency and Time Forum and IEEE International Frequency Control Symposium, EFTF/IFC 2017 - Proceedings

Other

Other2017 Joint Conference of the European Frequency and Time Forum and IEEE International Frequency Control Symposium, EFTF/IFC 2017
Country/TerritoryFrance
CityBesancon
Period7/9/177/13/17

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Instrumentation

Keywords

  • AT-cut TCXO oscillators
  • CMOS integration
  • Quartz MEMS
  • Stress isolation
  • Temperature compensation
  • Wafer-level vacuum packaging

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