TY - GEN
T1 - Advanced SOI substrate manufacturing
AU - Mazuré, C.
AU - Celler, G. K.
AU - Maleville, C.
AU - Cayrefourcq, I.
PY - 2004
Y1 - 2004
N2 - 300 mm SOI wafers with sub-100nm thick active Si layers are currently produced in large quantities and used in advanced microprocessor circuits. To further enhance the performance of the next generation of devices, strained Si layers on insulator are being developed. The lattice mismatch between silicon and SiGe alloys, combined with layer transfer through the Smart Cut™ technology allow forming two types of strained Si - strained Si on SiGe on insulator, known as SGOI, and strained Si directly on insulator, known as sSOI. Fabrication methods and wafer characteristics for SOI, SGOI, and sSOI are discussed here.
AB - 300 mm SOI wafers with sub-100nm thick active Si layers are currently produced in large quantities and used in advanced microprocessor circuits. To further enhance the performance of the next generation of devices, strained Si layers on insulator are being developed. The lattice mismatch between silicon and SiGe alloys, combined with layer transfer through the Smart Cut™ technology allow forming two types of strained Si - strained Si on SiGe on insulator, known as SGOI, and strained Si directly on insulator, known as sSOI. Fabrication methods and wafer characteristics for SOI, SGOI, and sSOI are discussed here.
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M3 - Conference contribution
AN - SCOPUS:4143125584
SN - 0780385284
T3 - 2004 International Conference on Integrated Circuit Design and Technology, ICICDT
SP - 105
EP - 111
BT - 2004 International Conference on Integrated Circuit Design and Technology, ICICDT
T2 - 2004 International Conference on Integrated Circuit Design and Technology, ICICDT
Y2 - 17 May 2004 through 20 May 2004
ER -