Architectural support for address translation on GPUs: Designing Memory Management Units for CPU/GPUs with unified address spaces

Bharath Pichai, Lisa Hsu, Abhishek Bhattacharjee

Research output: Chapter in Book/Report/Conference proceedingConference contribution

71 Scopus citations

Abstract

The proliferation of heterogeneous compute platforms, of which CPU/GPU is a prevalent example, necessitates a manageable programming model to ensure widespread adoption. A key component of this is a shared unified address space between the heterogeneous units to obtain the programmability benefits of virtual memory. To this end, we explore GPU Memory Management Units (MMUs) consisting of Translation Lookaside Buffers (TLBs) and page table walkers (PTWs) in unified heterogeneous systems.We show the challenges posed by GPU warp schedulers on TLBs accessed in parallel with L1 caches, which provide many well-known programmability benefits. In response, we propose modest TLB and PTW augmentations that recover most of the performance lost by introducing L1-parallel TLB access. We also show that a little TLB-awareness can make other GPU performance enhancements (e.g., cache-conscious warp scheduling and dynamic warp formation on branch divergence) feasible in the face of cache-parallel address translation, bringing overheads in the range deemed acceptable for CPUs (10-15% of runtime). We presume this initial design leaves room for improvement but anticipate the bigger insight, that a little TLB-awareness goes a long way in GPUs, will spur further work in this area.

Original languageEnglish (US)
Title of host publicationASPLOS 2014 - 19th International Conference on Architectural Support for Programming Languages and Operating Systems
Pages743-757
Number of pages15
DOIs
StatePublished - Mar 14 2014
Event19th International Conference on Architectural Support for Programming Languages and Operating Systems, ASPLOS 2014 - Salt Lake City, UT, United States
Duration: Mar 1 2014Mar 5 2014

Publication series

NameInternational Conference on Architectural Support for Programming Languages and Operating Systems - ASPLOS

Other

Other19th International Conference on Architectural Support for Programming Languages and Operating Systems, ASPLOS 2014
CountryUnited States
CitySalt Lake City, UT
Period3/1/143/5/14

All Science Journal Classification (ASJC) codes

  • Software
  • Information Systems
  • Hardware and Architecture

Keywords

  • GPUs
  • MMUs
  • TLBs
  • Unified address space

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    Pichai, B., Hsu, L., & Bhattacharjee, A. (2014). Architectural support for address translation on GPUs: Designing Memory Management Units for CPU/GPUs with unified address spaces. In ASPLOS 2014 - 19th International Conference on Architectural Support for Programming Languages and Operating Systems (pp. 743-757). (International Conference on Architectural Support for Programming Languages and Operating Systems - ASPLOS). https://doi.org/10.1145/2541940.2541942