Buried Channel MOSFET's with Gate Lengths from 2.5 μm to 700 Â

R. E. Howard; L. D. Jackel; R. G. Swartz; P. Grabbe; V. D. Archer; R. W. Epworth; E. L. Hu; D. M. Tennant; A. M. Voshchenkov

doi:10.1109/EDL.1982.25585

Buried Channel MOSFET's with Gate Lengths from 2.5 μm to 700 Â

R. E. Howard, L. D. Jackel, R. G. Swartz, P. Grabbe, V. D. Archer, R. W. Epworth, E. L. Hu, D. M. Tennant, A. M. Voshchenkov

Research output: Contribution to journal › Article › peer-review

8 Scopus citations

Abstract

High resolution electron beam lithography has been used to fabricate ion implanted buried channel MOSFET's with gate lengths ranging from 0.4 μm to 700 Â. Similar devices were also fabricated on the same chip using optical lithography with gate lengths of 2.5 μm. These devices include some with the smallest lithographically defined gates ever made in silicon; similar devices should help define the limits to miniaturization in semiconducting devices.

Original language	English (US)
Pages (from-to)	322-324
Number of pages	3
Journal	IEEE Electron Device Letters
Volume	3
Issue number	10
DOIs	https://doi.org/10.1109/EDL.1982.25585
State	Published - Oct 1982
Externally published	Yes

All Science Journal Classification (ASJC) codes

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

Access to Document

10.1109/EDL.1982.25585

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title = "Buried Channel MOSFET's with Gate Lengths from 2.5 μm to 700 {\^A}",

abstract = "High resolution electron beam lithography has been used to fabricate ion implanted buried channel MOSFET's with gate lengths ranging from 0.4 μm to 700 {\^A}. Similar devices were also fabricated on the same chip using optical lithography with gate lengths of 2.5 μm. These devices include some with the smallest lithographically defined gates ever made in silicon; similar devices should help define the limits to miniaturization in semiconducting devices.",

author = "Howard, {R. E.} and Jackel, {L. D.} and Swartz, {R. G.} and P. Grabbe and Archer, {V. D.} and Epworth, {R. W.} and Hu, {E. L.} and Tennant, {D. M.} and Voshchenkov, {A. M.}",

year = "1982",

month = oct,

doi = "10.1109/EDL.1982.25585",

language = "English (US)",

volume = "3",

pages = "322--324",

journal = "IEEE Electron Device Letters",

issn = "0741-3106",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "10",

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AU - Howard, R. E.

AU - Jackel, L. D.

AU - Swartz, R. G.

AU - Grabbe, P.

AU - Archer, V. D.

AU - Epworth, R. W.

AU - Hu, E. L.

AU - Tennant, D. M.

AU - Voshchenkov, A. M.

PY - 1982/10

Y1 - 1982/10

N2 - High resolution electron beam lithography has been used to fabricate ion implanted buried channel MOSFET's with gate lengths ranging from 0.4 μm to 700 Â. Similar devices were also fabricated on the same chip using optical lithography with gate lengths of 2.5 μm. These devices include some with the smallest lithographically defined gates ever made in silicon; similar devices should help define the limits to miniaturization in semiconducting devices.

AB - High resolution electron beam lithography has been used to fabricate ion implanted buried channel MOSFET's with gate lengths ranging from 0.4 μm to 700 Â. Similar devices were also fabricated on the same chip using optical lithography with gate lengths of 2.5 μm. These devices include some with the smallest lithographically defined gates ever made in silicon; similar devices should help define the limits to miniaturization in semiconducting devices.

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