Circuits over monoids: a fault model, and a trade-off between testability and circuit delay

H. A. Farhat; J. C. Birget

doi:10.1016/0893-9659(92)90064-G

Circuits over monoids: a fault model, and a trade-off between testability and circuit delay

Research output: Contribution to journal › Article › peer-review

Abstract

We introduce a new fault model for evaluation circuits and prefix circuits over a transformation monoid. For evaluation circuits we give a trade-off between the delay of the circuit and the number of test-inputs needed to detect faultiness.

Original language	English (US)
Pages (from-to)	55-58
Number of pages	4
Journal	Applied Mathematics Letters
Volume	5
Issue number	5
DOIs	https://doi.org/10.1016/0893-9659(92)90064-G
State	Published - Sep 1992
Externally published	Yes

All Science Journal Classification (ASJC) codes

Applied Mathematics

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10.1016/0893-9659(92)90064-G

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title = "Circuits over monoids: a fault model, and a trade-off between testability and circuit delay",

abstract = "We introduce a new fault model for evaluation circuits and prefix circuits over a transformation monoid. For evaluation circuits we give a trade-off between the delay of the circuit and the number of test-inputs needed to detect faultiness.",

author = "Farhat, {H. A.} and Birget, {J. C.}",

year = "1992",

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AU - Birget, J. C.

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Circuits over monoids: a fault model, and a trade-off between testability and circuit delay

Abstract

All Science Journal Classification (ASJC) codes

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