CoLT: Coalesced large-reach TLBs

Binh Pham, Viswanathan Vaidyanathan, Aamer Jaleel, Abhishek Bhattacharjee

Research output: Chapter in Book/Report/Conference proceedingConference contribution

121 Scopus citations

Abstract

Translation Look aside Buffers (TLBs) are critical to system performance, particularly as applications demand larger working sets and with the adoption of virtualization. Architectural support for super pages has previously been proposed to improve TLB performance. By allocating contiguous physical pages to contiguous virtual pages, the operating system (OS) constructs super pages which need just one TLB entry rather than the hundreds required for the constituent base pages. While this greatly reduces TLB misses, these gains are often offset by the implementation difficulties of generating and managing ample contiguity for super pages. We show, however, that basic OS memory allocation mechanisms such as buddy allocators and memory compaction naturally assign contiguous physical pages to contiguous virtual pages. Our real-system experiments show that while usually insufficient for super pages, these intermediate levels of contiguity exist under various system conditions and even under high load. In response, we propose Coalesced Large-Reach TLBs (CoLT), which leverage this intermediate contiguity to coalesce multiple virtual-to-physical page translations into single TLB entries. We show that CoLT implementations eliminate 40\% to 58\% of TLB misses on average, improving performance by 14\%. Overall, we demonstrate that the OS naturally generates page allocation contiguity. CoLT exploits this contiguity to eliminate TLB misses for next-generation, big-data applications with low-overhead implementations.

Original languageEnglish (US)
Title of host publicationProceedings - 2012 IEEE/ACM 45th International Symposium on Microarchitecture, MICRO 2012
Pages258-269
Number of pages12
DOIs
StatePublished - 2012
Event2012 IEEE/ACM 45th International Symposium on Microarchitecture, MICRO 2012 - Vancouver, BC, Canada
Duration: Dec 1 2012Dec 5 2012

Publication series

NameProceedings - 2012 IEEE/ACM 45th International Symposium on Microarchitecture, MICRO 2012

Other

Other2012 IEEE/ACM 45th International Symposium on Microarchitecture, MICRO 2012
Country/TerritoryCanada
CityVancouver, BC
Period12/1/1212/5/12

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture

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