Critical points based register-concurrency autotuning for GPUs

Ang Li, Shuaiwen Leon Song, Akash Kumar, Eddy Z. Zhang, Daniel Chavarría-Miranda, Henk Corporaal

Research output: Chapter in Book/Report/Conference proceedingConference contribution

10 Scopus citations

Abstract

The unprecedented prevalence of GPGPU is largely attributed to its abundant on-chip register resources, which allow massively concurrent threads and extremely fast context switch. However, due to internal memory size constraints, there is a tradeoff between the per-thread register usage and the overall thread concurrency. This becomes a design problem in terms of performance tuning, since the performance sweet spot which can be significantly affected by these two factors is generally unknown beforehand. In this paper, we propose an effective autotuning solution to quickly and efficiently select the optimal number of registers perthread for delivering the best GPU performance. Experiments on three generations of GPUs (Nvidia Fermi, Kepler and Maxwell) demonstrate that our simple strategy can achieve an average of 10% performance improvement while a max of 50% over the original version without modifying the user code. Additionally, to reduce local cache misses due to register spilling and further improve performance, we explore three optimization schemes (i.e. bypass L1 for global memory access, enlarge local L1 cache and spill into shared memory) and discuss their impact on performance on a Kepler GPU.

Original languageEnglish (US)
Title of host publicationProceedings of the 2016 Design, Automation and Test in Europe Conference and Exhibition, DATE 2016
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages1273-1278
Number of pages6
ISBN (Electronic)9783981537062
StatePublished - Apr 25 2016
Event19th Design, Automation and Test in Europe Conference and Exhibition, DATE 2016 - Dresden, Germany
Duration: Mar 14 2016Mar 18 2016

Publication series

NameProceedings of the 2016 Design, Automation and Test in Europe Conference and Exhibition, DATE 2016

Other

Other19th Design, Automation and Test in Europe Conference and Exhibition, DATE 2016
CountryGermany
CityDresden
Period3/14/163/18/16

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Safety, Risk, Reliability and Quality

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