TY - GEN
T1 - Decoding CUDA Binary
AU - Hayes, Ari B.
AU - Hua, Fei
AU - Huang, Jin
AU - Chen, Yanhao
AU - Zhang, Eddy Z.
N1 - Publisher Copyright:
© 2019 IEEE.
PY - 2019/3/5
Y1 - 2019/3/5
N2 - NVIDIA's software does not offer translation of assembly code to binary for their GPUs, since the specifications are closed-source. This work fills that gap. We develop a systematic method of decoding the Instruction Set Architectures (ISAs) of NVIDIA's GPUs, and generating assemblers for different generations of GPUs. Our framework enables cross-architecture binary analysis and transformation. Making the ISA accessible in this manner opens up a world of opportunities for developers and researchers, enabling numerous optimizations and explorations that are unachievable at the source-code level. Our infrastructure has already benefited and been adopted in important applications including performance tuning, binary instrumentation, resource allocation, and memory protection.
AB - NVIDIA's software does not offer translation of assembly code to binary for their GPUs, since the specifications are closed-source. This work fills that gap. We develop a systematic method of decoding the Instruction Set Architectures (ISAs) of NVIDIA's GPUs, and generating assemblers for different generations of GPUs. Our framework enables cross-architecture binary analysis and transformation. Making the ISA accessible in this manner opens up a world of opportunities for developers and researchers, enabling numerous optimizations and explorations that are unachievable at the source-code level. Our infrastructure has already benefited and been adopted in important applications including performance tuning, binary instrumentation, resource allocation, and memory protection.
KW - CUDA
KW - Code Generation
KW - Code Translation and Transformation
KW - GPU
KW - Instruction Set Architecture (ISA)
UR - http://www.scopus.com/inward/record.url?scp=85063814807&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85063814807&partnerID=8YFLogxK
U2 - 10.1109/CGO.2019.8661186
DO - 10.1109/CGO.2019.8661186
M3 - Conference contribution
AN - SCOPUS:85063814807
T3 - CGO 2019 - Proceedings of the 2019 IEEE/ACM International Symposium on Code Generation and Optimization
SP - 229
EP - 241
BT - CGO 2019 - Proceedings of the 2019 IEEE/ACM International Symposium on Code Generation and Optimization
A2 - Moseley, Tipp
A2 - Jimborean, Alexandra
A2 - Kandemir, Mahmut Taylan
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 17th IEEE/ACM International Symposium on Code Generation and Optimization, CGO 2019
Y2 - 16 February 2019 through 20 February 2019
ER -