Decoding CUDA Binary

Ari B. Hayes, Fei Hua, Jin Huang, Yanhao Chen, Eddy Z. Zhang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

12 Scopus citations

Abstract

NVIDIA's software does not offer translation of assembly code to binary for their GPUs, since the specifications are closed-source. This work fills that gap. We develop a systematic method of decoding the Instruction Set Architectures (ISAs) of NVIDIA's GPUs, and generating assemblers for different generations of GPUs. Our framework enables cross-architecture binary analysis and transformation. Making the ISA accessible in this manner opens up a world of opportunities for developers and researchers, enabling numerous optimizations and explorations that are unachievable at the source-code level. Our infrastructure has already benefited and been adopted in important applications including performance tuning, binary instrumentation, resource allocation, and memory protection.

Original languageEnglish (US)
Title of host publicationCGO 2019 - Proceedings of the 2019 IEEE/ACM International Symposium on Code Generation and Optimization
EditorsTipp Moseley, Alexandra Jimborean, Mahmut Taylan Kandemir
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages229-241
Number of pages13
ISBN (Electronic)9781728114361
DOIs
StatePublished - Mar 5 2019
Event17th IEEE/ACM International Symposium on Code Generation and Optimization, CGO 2019 - Washington, United States
Duration: Feb 16 2019Feb 20 2019

Publication series

NameCGO 2019 - Proceedings of the 2019 IEEE/ACM International Symposium on Code Generation and Optimization

Conference

Conference17th IEEE/ACM International Symposium on Code Generation and Optimization, CGO 2019
Country/TerritoryUnited States
CityWashington
Period2/16/192/20/19

All Science Journal Classification (ASJC) codes

  • Software
  • Control and Optimization

Keywords

  • CUDA
  • Code Generation
  • Code Translation and Transformation
  • GPU
  • Instruction Set Architecture (ISA)

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