Design of a novel planar normally-off power VJFET in 4H-SiC

J. H. Zhao, X. Li, K. Tone, P. Alexandrov, M. Pan, M. Weiner

Research output: Contribution to journalArticlepeer-review

18 Scopus citations


In this paper, a novel planar high-voltage normally-off 4H-SiC vertical JFET (P-VJFET) is proposed and modeled by way of two-dimensional numerical simulations. The proposed P-VJFET is based on the monolithic combination of a low voltage lateral JFET (LJFET) and a high voltage vertical JFET. By designing the LJFET to be normally-off, the P-VJFET becomes a normally-off switch without requiring a submicron vertical channel opening which is difficult to achieve by photolithographic means, coupled with the need of multi-MeV ion implantation. The P-VJFETs DC and switching characteristics are investigated at 300 and 600 K. A structure with a 12 μm 6.8 × 1015 cm-3 doped drift layer is simulated, showing blocking voltages of 1644 and 1928 V with specific on-resistances of 4.8 and 19.6 mΩ cm2 at 300 and 600 K, respectively. With a dVG/dt rate of 1 × 108 V/s, the normally-off P-VJFET is able to switch a drain current density of 100 A/cm2 with a turn-on time of 24 ns and a turn-off time of 40 ns. Since there is no gate oxide/insulator, the proposed normally-off P-VJFET is expected to be advantageous in comparison to MOSFET-based SiC power switches for high temperature operation.

Original languageEnglish (US)
Pages (from-to)377-384
Number of pages8
JournalSolid-State Electronics
Issue number2
StatePublished - Feb 2003

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics
  • Electrical and Electronic Engineering
  • Materials Chemistry


  • High temperature
  • Numerical simulation
  • SiC
  • Vertical JFET


Dive into the research topics of 'Design of a novel planar normally-off power VJFET in 4H-SiC'. Together they form a unique fingerprint.

Cite this