Designing systolic algorithms using sequential machines

We offer a methodology for simplifying the design and analysis of systolic systems. Speciflcally, we give characterizations of systolic arrays in terms of (single processor) sequential machines which are easier to analyze and to program. We give several examples to illustrate the design methodology. In particular, we show how systolic arrays can be easily designed to implement priority queues, integer bitwise multiplication, dynamic programming, etc.. Because the designs are based on the sequential machine, the constructions we obtain are much simpler than those that have appeared in the literature. We also give some results concerning the properties and computational power (e.g., speed-up, hierarchy, etc.) of systolic arrays.