Engineering substrates for 3d integration of iii-v and CMOS

K. J. Herrick, T. E. Kazior, J. Laroche, A. W.K. Liu, D. Lubyshev, J. M. Fastenau, M. Urteaga, W. Ha, J. Bergman, B. Brar, M. T. Bulsara, E. A. Fitzgerald, D. Clark, D. Smith, R. F. Thompson, N. Daval, G. K. Celler

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Scopus citations


Our direct growth approach of integrating compound semiconductors (CS) and silicon CMOS is based on a unique silicon template wafer with an embedded CS template layer of Germanium (Ge). It enables selective placement of CS devices in arbitrary locations on a Silicon CMOS wafer for simple, high yield, monolithic integration and optimal circuit performance. HBTs demonstrate a peak current gain cutoff frequency ft over 200 GHz. To the best of our knowledge this represents the first demonstration of an InP-based HBT fabricated on a silicon wafer.

Original languageEnglish (US)
Title of host publicationECS Transactions - Semiconductor Wafer Bonding 10
Subtitle of host publicationScience, Technology, and Applications
PublisherElectrochemical Society Inc.
Number of pages8
ISBN (Print)9781566776547
StatePublished - 2009
Externally publishedYes
EventSemiconductor Wafer Bonding 10: Science, Technology, and Applications - 214th ECS Meeting - Honolulu, HI, United States
Duration: Oct 14 2008Oct 16 2008

Publication series

NameECS Transactions
ISSN (Print)1938-5862
ISSN (Electronic)1938-6737


OtherSemiconductor Wafer Bonding 10: Science, Technology, and Applications - 214th ECS Meeting
Country/TerritoryUnited States
CityHonolulu, HI

All Science Journal Classification (ASJC) codes

  • Engineering(all)


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