Abstract
The increasing gap between the rate at which large scale scientific simulations generate data and the corresponding storage speeds and capacities is leading to more complex system architectures with deep memory hierarchies. Advances in non-volatile memory (NVRAM) technology have made it an attractive candidate as intermediate storage in this memory hierarchy to address the latency and performance gap between main memory and disk storage. As a result, it is important to understand and model its energy/performance behavior from an application perspective as well as how it can be effectively used for staging data within an application workflow. In this paper, we target a NVRAM-based deep memory hierarchy and explore its potential for supporting in-situ/in-transit data analytics pipelines that are part of application workflows patterns. Specifically, we model the memory hierarchy and experimentally explore energy/performance behaviors of different data management strategies and data exchange patterns, as well as the tradeoffs associated with data placement, data movement and data processing.
Original language | English (US) |
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Pages | 226-235 |
Number of pages | 10 |
DOIs | |
State | Published - 2013 |
Event | 20th Annual International Conference on High Performance Computing, HiPC 2013 - Bangalore, India Duration: Dec 18 2013 → Dec 21 2013 |
Other
Other | 20th Annual International Conference on High Performance Computing, HiPC 2013 |
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Country/Territory | India |
City | Bangalore |
Period | 12/18/13 → 12/21/13 |
All Science Journal Classification (ASJC) codes
- Software