FPGA-accelerated simulation of a hybrid-ARQ system using high level synthesis

Swapnil Mhaske, Hojin Kee, Tai Ly, Predrag Spasojevic

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Scopus citations

Abstract

Physical layer processing for 5G wireless is expected to operate at a very high-throughput with very low latency. Developing a channel coding system based on Hybrid Automatic Repeat reQuest (HARQ) for evolving requirements necessitates extensive experimentation involving undesirably long development cycles. We demonstrate the use of a High-level Synthesis (HLS) compiler in LabVIEW Communications to prototype a real world HARQ system using Low-Density Parity-Check (LDPC) codes, however, without the expertise of an Hardware Description Language (HDL) designer. This implementation consumed 54% of the resources on our FPGA and allowed us to measure error-rate performance of the system over large, realistic data sets using accelerated, in-hardware simulation with a system throughput that is 4× greater than the CPU-based implementation. Furthermore, use of the HLS methodology significantly reduced time to explore the HARQ system parameter space and optimize in terms of error-rate performance and resource utilization.

Original languageEnglish (US)
Title of host publication37th IEEE Sarnoff Symposium, Sarnoff 2016
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages19-24
Number of pages6
ISBN (Electronic)9781509015405
DOIs
StatePublished - Feb 7 2017
Event37th IEEE Sarnoff Symposium, Sarnoff 2016 - Newark, United States
Duration: Sep 19 2016Sep 21 2016

Publication series

Name37th IEEE Sarnoff Symposium, Sarnoff 2016

Other

Other37th IEEE Sarnoff Symposium, Sarnoff 2016
Country/TerritoryUnited States
CityNewark
Period9/19/169/21/16

All Science Journal Classification (ASJC) codes

  • Computer Networks and Communications
  • Hardware and Architecture

Keywords

  • 5G
  • HARQ
  • HLS
  • Intellectual Property (IP)
  • QC-LDPC

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