TY - JOUR
T1 - Gate characterization using singular value decomposition
T2 - Foundations and applications
AU - Wei, Sheng
AU - Nahapetian, Ani
AU - Nelson, Michael
AU - Koushanfar, Farinaz
AU - Potkonjak, Miodrag
N1 - Funding Information:
Manuscript received April 15, 2011; revised October 06, 2011; accepted December 04, 2011. Date of publication December 23, 2011; date of current version March 08, 2012. This work was supported in part by the NSF under Award CNS-0958369, Award CNS-1059435, and Award CCF-0926127. This paper was presented in part at the 11th Information Hiding Conference (IH 2009). The associate editor coordinating the review of this manuscript and approving it for publication was Dr. Ramesh Karri.
PY - 2012/4
Y1 - 2012/4
N2 - Modern hardware security has a very broad scope ranging from digital rights management to the detection of ghost circuitry. These and many other security tasks are greatly hindered by process variation, which makes each integrated circuit (IC) unique, and device aging, which evolves the IC throughout its lifetime. We have developed a singular value decomposition (SVD)-based procedure for gate-level characterization (GLC) that calculates changes in properties, such as delay and switching power of each gate of an IC, accounting for process variation and device aging. We employ our SVD-based GLC approach for the development of two security applications: hardware metering and ghost circuitry (GC) detection. We present the first robust and low-cost hardware metering scheme, using an overlapping IC partitioning approach that enables rapid and scalable treatment. We also map the GC detection problem into an equivalent task of GLC consistency checking using the same overlapping partitioning. The effectiveness of the approaches is evaluated using the ISCAS85, ISCAS89, and ITC99 benchmarks. In hardware metering, we are able to obtain probabilities of coincidence in the magnitude of 10 -8 or less, and we obtain zero false positives and zero false negatives in GC detection.
AB - Modern hardware security has a very broad scope ranging from digital rights management to the detection of ghost circuitry. These and many other security tasks are greatly hindered by process variation, which makes each integrated circuit (IC) unique, and device aging, which evolves the IC throughout its lifetime. We have developed a singular value decomposition (SVD)-based procedure for gate-level characterization (GLC) that calculates changes in properties, such as delay and switching power of each gate of an IC, accounting for process variation and device aging. We employ our SVD-based GLC approach for the development of two security applications: hardware metering and ghost circuitry (GC) detection. We present the first robust and low-cost hardware metering scheme, using an overlapping IC partitioning approach that enables rapid and scalable treatment. We also map the GC detection problem into an equivalent task of GLC consistency checking using the same overlapping partitioning. The effectiveness of the approaches is evaluated using the ISCAS85, ISCAS89, and ITC99 benchmarks. In hardware metering, we are able to obtain probabilities of coincidence in the magnitude of 10 -8 or less, and we obtain zero false positives and zero false negatives in GC detection.
KW - Gate-level characteristics
KW - ghost circuitry
KW - hardware metering
KW - process variation
KW - singular value decomposition
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U2 - 10.1109/TIFS.2011.2181500
DO - 10.1109/TIFS.2011.2181500
M3 - Article
AN - SCOPUS:84858386088
SN - 1556-6013
VL - 7
SP - 765
EP - 773
JO - IEEE Transactions on Information Forensics and Security
JF - IEEE Transactions on Information Forensics and Security
IS - 2
M1 - 6112216
ER -