High-speed area-efficient versatile Reed-Solomon decoder design for multi-mode applications

Bo Yuan, Li Li, Zhongfeng Wang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

In current high-speed communication and storage systems, the increasing demand for providing flexible Reed-Solomon (RS) decoding solutions to multi-mode applications has created the desire of universal RS decoders. In this paper, we present a high-speed area-efficient versatile RS decoder architecture based on recursive degree computationless modified Euclidean (rDCME) algorithm. Targeting at different practical applications, the proposed architecture is developed into two universal RS decoder designs. Arithmetic modification to Montgomery multiplication is exploited for the reduction of area. Compared with existing works, the proposed configurable designs can deliver higher data rate with relatively lower hardware complexity, thus they are good candidates for high-speed multi-mode applications.

Original languageEnglish (US)
Title of host publication2009 IEEE Workshop on Signal Processing Systems, SiPS 2009 - Proceedings
Pages179-184
Number of pages6
DOIs
StatePublished - Dec 1 2009
Externally publishedYes
Event2009 IEEE Workshop on Signal Processing Systems, SiPS 2009 - Tampere, Finland
Duration: Oct 7 2009Oct 9 2009

Publication series

NameIEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation
ISSN (Print)1520-6130

Other

Other2009 IEEE Workshop on Signal Processing Systems, SiPS 2009
CountryFinland
CityTampere
Period10/7/0910/9/09

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering
  • Signal Processing
  • Applied Mathematics
  • Hardware and Architecture

Keywords

  • Degree computationless
  • Modified Euclidean algorithm
  • Reed-Solomon (RS) codes
  • VLSI architecture
  • Versatile

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