High-speed Reed-Solomon errors-and-erasures decoder design with burst error correcting

Reed-Solomon code has been extensively studied in both academia and industry for its wide applications in digital communication and data storage systems. However, existing works are focused on errors-alone or errors-and-erasures decoding. In this paper, starting from a recent theoretical work, an efficient VLSI architecture is developed and implemented by exploring pipeline-interleaving inversionless Berlekamp-Massey algorithm, which not only keeps original RS code's error or error-and-erasure correcting capability, but also has significantly improved burst error correcting capacity. The new architecture, denoted as PI-iBM-BEC, is shown to achieve better error correcting capacity and delivers higher throughput with relatively lower hardware complexity compared with prior arts¹.