Increasing TLB reach by exploiting clustering in page translations

Binh Pham, Abhishek Bhattacharjee, Yasuko Eckert, Gabriel H. Loh

Research output: Chapter in Book/Report/Conference proceedingConference contribution

116 Scopus citations

Abstract

The steadily increasing sizes of main memory capacities require corresponding increases in the processor's translation lookaside buffer (TLB) resources to avoid performance bottlenecks. Large operating system page sizes can mitigate the bottleneck with a smaller TLB, but most OSs and applications do not fully utilize the large-page support in current hardware. Recent work has shown that, while not guaranteed, some virtual-to-physical page mappings exhibit 'contiguous' spatial locality in which consecutive virtual pages map to consecutive physical pages. Such locality provides opportunities to coalesce 'adjacent' TLB entries for increased reach. We observe that beyond simple adjacent-entry coalescing, many more translations exhibit 'clustered' spatial locality in which a group or cluster of nearby virtual pages map to a similarly clustered set of physical pages. In this work, we provide a detailed characterization of the spatial locality among the virtual-to-physical translations. Based on this characterization, we present a multi-granular TLB organization that significantly increases its effective reach and reduces miss rates substantially while requiring no additional OS support. Our evaluation shows that the multi-granular design outperforms conventional TLBs and the recently proposed coalesced TLBs technique.

Original languageEnglish (US)
Title of host publication20th IEEE International Symposium on High Performance Computer Architecture, HPCA 2014
PublisherIEEE Computer Society
Pages558-567
Number of pages10
ISBN (Print)9781479930975
DOIs
StatePublished - 2014
Event20th IEEE International Symposium on High Performance Computer Architecture, HPCA 2014 - Orlando, FL, United States
Duration: Feb 15 2014Feb 19 2014

Publication series

NameProceedings - International Symposium on High-Performance Computer Architecture
ISSN (Print)1530-0897

Other

Other20th IEEE International Symposium on High Performance Computer Architecture, HPCA 2014
Country/TerritoryUnited States
CityOrlando, FL
Period2/15/142/19/14

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture

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