N-type, top gate, single-crystal Si thin-film transistors (TFTs) using evaporated silicon monoxide (SiO) as the gate dielectric layer are fabricated on flexible plastic substrate. The threshold voltage (VT) instability of the device is studied by applying high gate voltages. VT shift to higher values under positive gate bias stress is observed. The logarithmic dependence of VT shift on time indicates that electrons are injected and trapped in the SiO layer from Si channel. The subthreshold swing degradation is also found after the stress, suggesting the generation of interface states at Si/SiO surface. However, under negative gate stress, VT firstly decreases and then increases after longer stress time. This is believed to be the combined effects of both holes injection from Si substrate and electrons emission from metal gate, for which the latter become dominant under a long-term stress.