Is your low power design switched on?

Mark Croft, Stephen Bailey

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Scopus citations


Power is the key driver in most electronic systems design. Managing system power to increase battery life and reduce electricity consumption and heat generation are key considerations in developing many types of systems from mobile handsets, portable navigation systems and compute servers. New design techniques including clock gating, power gating, multi-voltage and dynamic voltage and frequency scaling have been employed to reduce both dynamic and static energy consumption. The design of low power electronic systems creates new design and verification challenges. Today's systems-on-chip are composed of large IP blocks approaching and exceeding 1 million gates. How can the system low power design intent be applied without requiring modification to and time consuming re-verification of the IP's golden RTL code? How can the functional impacts of power gating, retention and isolation be verified early in the design process when it is cheaper and easier to fix problems? Can implementation- dependent low power design functionality such as accurate retention save and restore protocols be verified prior to synthesis? In this presentation, we will discuss Accellera's Unified Power Format standard for low power design intent and using UPF for verification.

Original languageEnglish (US)
Title of host publication2007 International Symposium on System-on-Chip Proceedings, SOC
StatePublished - 2007
Externally publishedYes
Event2007 International Symposium on System-on-Chip, SOC - Tampere, Finland
Duration: Nov 20 2007Nov 21 2007

Publication series

Name2007 International Symposium on System-on-Chip Proceedings, SOC


Other2007 International Symposium on System-on-Chip, SOC

All Science Journal Classification (ASJC) codes

  • Control and Systems Engineering
  • Electrical and Electronic Engineering

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