Low-cost hardware acceleration for volume visualization

Michael Dao; Todd A. Cook; Deborah E. Silver

Low-cost hardware acceleration for volume visualization

Michael Dao, Todd A. Cook, Deborah E. Silver

School of Engineering, Electrical & Computer Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

1 Scopus citations

Abstract

Volume visualization is a popular method for viewing simulated or experimental 3D data sets from applications such as medical imaging, computational fluid dynamics, and climate modeling. However, most software and low-cost hardware implementations of visualization algorithms do not have sufficient performance for inter-active viewing. This paper discusses a method for low-cost, parallel hardware acceleration of volume rendering using a PC-hosted FPGA board. Our method uses a parallel distributed memory approach for compositing and tranformation of volume data, and it provides insight into efficient use of low-cost memory systems.

Original language	English (US)
Title of host publication	Proceedings of SPIE - The International Society for Optical Engineering
Pages	104-114
Number of pages	11
State	Published - 1995
Event	Field Programmable Gate Arrays (FPGAs) for Fast Board Development and Reconfigurable Computing - Philadelphia, PA, USA Duration: Oct 25 1995 → Oct 26 1995

Publication series

Name	Proceedings of SPIE - The International Society for Optical Engineering
Volume	2607
ISSN (Print)	0277-786X

Other

Other	Field Programmable Gate Arrays (FPGAs) for Fast Board Development and Reconfigurable Computing
City	Philadelphia, PA, USA
Period	10/25/95 → 10/26/95

All Science Journal Classification (ASJC) codes

Electronic, Optical and Magnetic Materials
Condensed Matter Physics
Computer Science Applications
Applied Mathematics
Electrical and Electronic Engineering

Cite this

@inproceedings{9949127e2f104663987432d8d409dd82,

title = "Low-cost hardware acceleration for volume visualization",

abstract = "Volume visualization is a popular method for viewing simulated or experimental 3D data sets from applications such as medical imaging, computational fluid dynamics, and climate modeling. However, most software and low-cost hardware implementations of visualization algorithms do not have sufficient performance for inter-active viewing. This paper discusses a method for low-cost, parallel hardware acceleration of volume rendering using a PC-hosted FPGA board. Our method uses a parallel distributed memory approach for compositing and tranformation of volume data, and it provides insight into efficient use of low-cost memory systems.",

author = "Michael Dao and Cook, {Todd A.} and Silver, {Deborah E.}",

year = "1995",

language = "English (US)",

isbn = "0819419710",

series = "Proceedings of SPIE - The International Society for Optical Engineering",

pages = "104--114",

booktitle = "Proceedings of SPIE - The International Society for Optical Engineering",

note = "Field Programmable Gate Arrays (FPGAs) for Fast Board Development and Reconfigurable Computing ; Conference date: 25-10-1995 Through 26-10-1995",

}

Dao, M, Cook, TA & Silver, DE 1995, Low-cost hardware acceleration for volume visualization. in Proceedings of SPIE - The International Society for Optical Engineering. Proceedings of SPIE - The International Society for Optical Engineering, vol. 2607, pp. 104-114, Field Programmable Gate Arrays (FPGAs) for Fast Board Development and Reconfigurable Computing, Philadelphia, PA, USA, 10/25/95.

Low-cost hardware acceleration for volume visualization. / Dao, Michael; Cook, Todd A.; Silver, Deborah E.

Proceedings of SPIE - The International Society for Optical Engineering. 1995. p. 104-114 (Proceedings of SPIE - The International Society for Optical Engineering; Vol. 2607).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - Low-cost hardware acceleration for volume visualization

AU - Dao, Michael

AU - Cook, Todd A.

AU - Silver, Deborah E.

PY - 1995

Y1 - 1995

N2 - Volume visualization is a popular method for viewing simulated or experimental 3D data sets from applications such as medical imaging, computational fluid dynamics, and climate modeling. However, most software and low-cost hardware implementations of visualization algorithms do not have sufficient performance for inter-active viewing. This paper discusses a method for low-cost, parallel hardware acceleration of volume rendering using a PC-hosted FPGA board. Our method uses a parallel distributed memory approach for compositing and tranformation of volume data, and it provides insight into efficient use of low-cost memory systems.

AB - Volume visualization is a popular method for viewing simulated or experimental 3D data sets from applications such as medical imaging, computational fluid dynamics, and climate modeling. However, most software and low-cost hardware implementations of visualization algorithms do not have sufficient performance for inter-active viewing. This paper discusses a method for low-cost, parallel hardware acceleration of volume rendering using a PC-hosted FPGA board. Our method uses a parallel distributed memory approach for compositing and tranformation of volume data, and it provides insight into efficient use of low-cost memory systems.

UR - http://www.scopus.com/inward/record.url?scp=0029493350&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0029493350&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:0029493350

SN - 0819419710

SN - 9780819419712

T3 - Proceedings of SPIE - The International Society for Optical Engineering

SP - 104

EP - 114

BT - Proceedings of SPIE - The International Society for Optical Engineering

T2 - Field Programmable Gate Arrays (FPGAs) for Fast Board Development and Reconfigurable Computing

Y2 - 25 October 1995 through 26 October 1995

ER -

Low-cost hardware acceleration for volume visualization

Abstract

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All Science Journal Classification (ASJC) codes

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