Abstract
Gate-level characterization (GLC) is the process of quantifying physical and manifestational properties for each gate of an integrated circuit (IC). It is a key step in many IC applications that target cryptography, security, digital rights management, low power, and yield optimization. However, GLC is a challenging task due to the size and structure of modern circuits and insufficient controllability of a subset of gates in the circuit. We have developed a new approach for GLC that employs thermal conditioning to calculate the scaling factors of all the gates by solving a system of linear equations using linear programming (LP). Therefore, the procedure captures the complete impact of process variation (PV). In order to resolve the correlations in the system of linear equations, we expose different gates to different temperatures and thus change their corresponding linear coefficients in the linear equations. We further improve the accuracy of GLC by applying statistical methods in the LP formulation as well as the post-processing steps. In order to enable non-destructive hardware Trojan horse (HTH) detection, we generalize our generic GLC procedure by manipulating the constraint of each linear equation. Furthermore, we ensure the scalability of the approaches for GLC and HTH detection using iterative IC segmentation. We evaluate our approach on a set of ISCAS and ITC benchmarks.
| Original language | English (US) |
|---|---|
| Article number | 5772002 |
| Pages (from-to) | 1136-1145 |
| Number of pages | 10 |
| Journal | IEEE Transactions on Information Forensics and Security |
| Volume | 6 |
| Issue number | 3 PART 2 |
| DOIs | |
| State | Published - Sep 1 2011 |
Fingerprint
All Science Journal Classification (ASJC) codes
- Safety, Risk, Reliability and Quality
- Computer Networks and Communications
Keywords
- Gate-level characterization (GLC)
- hardware Trojans
- process variation
Cite this
}
Malicious circuitry detection using thermal conditioning. / Wei, Sheng; Meguerdichian, Saro; Potkonjak, Miodrag.
In: IEEE Transactions on Information Forensics and Security, Vol. 6, No. 3 PART 2, 5772002, 01.09.2011, p. 1136-1145.Research output: Contribution to journal › Article
TY - JOUR
T1 - Malicious circuitry detection using thermal conditioning
AU - Wei, Sheng
AU - Meguerdichian, Saro
AU - Potkonjak, Miodrag
PY - 2011/9/1
Y1 - 2011/9/1
N2 - Gate-level characterization (GLC) is the process of quantifying physical and manifestational properties for each gate of an integrated circuit (IC). It is a key step in many IC applications that target cryptography, security, digital rights management, low power, and yield optimization. However, GLC is a challenging task due to the size and structure of modern circuits and insufficient controllability of a subset of gates in the circuit. We have developed a new approach for GLC that employs thermal conditioning to calculate the scaling factors of all the gates by solving a system of linear equations using linear programming (LP). Therefore, the procedure captures the complete impact of process variation (PV). In order to resolve the correlations in the system of linear equations, we expose different gates to different temperatures and thus change their corresponding linear coefficients in the linear equations. We further improve the accuracy of GLC by applying statistical methods in the LP formulation as well as the post-processing steps. In order to enable non-destructive hardware Trojan horse (HTH) detection, we generalize our generic GLC procedure by manipulating the constraint of each linear equation. Furthermore, we ensure the scalability of the approaches for GLC and HTH detection using iterative IC segmentation. We evaluate our approach on a set of ISCAS and ITC benchmarks.
AB - Gate-level characterization (GLC) is the process of quantifying physical and manifestational properties for each gate of an integrated circuit (IC). It is a key step in many IC applications that target cryptography, security, digital rights management, low power, and yield optimization. However, GLC is a challenging task due to the size and structure of modern circuits and insufficient controllability of a subset of gates in the circuit. We have developed a new approach for GLC that employs thermal conditioning to calculate the scaling factors of all the gates by solving a system of linear equations using linear programming (LP). Therefore, the procedure captures the complete impact of process variation (PV). In order to resolve the correlations in the system of linear equations, we expose different gates to different temperatures and thus change their corresponding linear coefficients in the linear equations. We further improve the accuracy of GLC by applying statistical methods in the LP formulation as well as the post-processing steps. In order to enable non-destructive hardware Trojan horse (HTH) detection, we generalize our generic GLC procedure by manipulating the constraint of each linear equation. Furthermore, we ensure the scalability of the approaches for GLC and HTH detection using iterative IC segmentation. We evaluate our approach on a set of ISCAS and ITC benchmarks.
KW - Gate-level characterization (GLC)
KW - hardware Trojans
KW - process variation
UR - http://www.scopus.com/inward/record.url?scp=80051746290&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=80051746290&partnerID=8YFLogxK
U2 - 10.1109/TIFS.2011.2157341
DO - 10.1109/TIFS.2011.2157341
M3 - Article
VL - 6
SP - 1136
EP - 1145
JO - IEEE Transactions on Information Forensics and Security
JF - IEEE Transactions on Information Forensics and Security
SN - 1556-6013
IS - 3 PART 2
M1 - 5772002
ER -