Scalable distributed last-level TLBs using low-latency interconnects

Srikant Bharadwaj, Guilherme Cox, Tushar Krishna, Abhishek Bhattacharjee

Research output: Chapter in Book/Report/Conference proceedingConference contribution

9 Scopus citations

Abstract

Recent studies have shown the potential of last-level TLBs shared by multiple cores in tackling memory translation performance challenges posed by 'big data' workloads. A key stumbling block hindering their effectiveness, however, is their high access time. We present a design methodology to reduce these high access times so as to realize high-performance and scalable shared L2 TLBs. As a first step, we study the benefits of replacing monolithic shared TLBs with a distributed set of small TLB slices. While this approach does reduce TLB lookup latency, it increases interconnect delays in accessing remote slices. Therefore, as a second step, we devise a lightweight single-cycle interconnect among the TLB slices by tailoring wires and switches to the unique communication characteristics of memory translation requests and responses. Our approach, which we dub Nocstar (NOCs for scalable TLB architecture), combines the high hit rates of shared TLBs with low access times of private L2 TLBs, enabling significant system performance benefits.

Original languageEnglish (US)
Title of host publicationProceedings - 51st Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2018
PublisherIEEE Computer Society
Pages271-284
Number of pages14
ISBN (Electronic)9781538662403
DOIs
StatePublished - Dec 12 2018
Event51st Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2018 - Fukuoka, Japan
Duration: Oct 20 2018Oct 24 2018

Publication series

NameProceedings of the Annual International Symposium on Microarchitecture, MICRO
Volume2018-October
ISSN (Print)1072-4451

Other

Other51st Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2018
Country/TerritoryJapan
CityFukuoka
Period10/20/1810/24/18

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture

Keywords

  • Caches
  • Network-on-chip
  • TLB
  • Virtual memory

Fingerprint

Dive into the research topics of 'Scalable distributed last-level TLBs using low-latency interconnects'. Together they form a unique fingerprint.

Cite this