Starting materials and functional layers for the 2005 international technology roadmap for semiconductors: Challenges and opportunities

Howard R. Huff, David Myers, Mike Walden, Larry Beckwith, Neil Weaver, George Celler, Bob Standley, Mayank T. Bulsara

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Scopus citations

Abstract

The integrated circuit (IC) industry is in the midst of an explosive expansion of new materials, processes and tools utilized in the fabrication of ICs and, accordingly, there are a host of associated new challenges and opportunities. These include, for example, the implementation of 300mm diameter wafers, the drive to equivalent oxide thickness in the sub-1.0 nanometer regime for high-performance logic devices via high-k gate-dielectric materials and metal gate electrodes, strained silicon methodologies, the expanded utilization of silicon-on-insulator (SOI) materials, copper metallization, low-k inter-level dielectrics and a plethora of alternative transistor configurations in non-classical CMOS device structures. We will discuss the implications of these advanced materials and device configurations on the International Technology Roadmap for Semiconductors (ITRS).

Original languageEnglish (US)
Title of host publicationCHARACTERIZATION AND METROLOGY FOR ULSI TECHNOLOGY 2005 - International Conference
Pages39-50
Number of pages12
DOIs
StatePublished - Sep 9 2005
Externally publishedYes
Event2005 International Conference on Characterization and Metrology for ULSI Technology - Richardson, TX, United States
Duration: Mar 15 2005Mar 18 2005

Publication series

NameAIP Conference Proceedings
Volume788
ISSN (Print)0094-243X
ISSN (Electronic)1551-7616

Other

Other2005 International Conference on Characterization and Metrology for ULSI Technology
Country/TerritoryUnited States
CityRichardson, TX
Period3/15/053/18/05

All Science Journal Classification (ASJC) codes

  • Physics and Astronomy(all)

Keywords

  • 450mm Silicon
  • ERO
  • Edge exclusion
  • ITRS
  • Particle size
  • SOI
  • Strained silicon
  • Wafer flatness

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