The design, implementation, and evaluation of a compiler algorithm for CPU energy reduction

Chung Hsing Hsu, Ulrich Kremer

Research output: Contribution to journalConference articlepeer-review

104 Scopus citations


This paper presents the design and implementation of a compiler algorithm that effectively optimizes programs for energy usage using dynamic voltage scaling (DVS). The algorithm identifies program regions where the CPU can be slowed down with negligible performance loss. It is implemented as a source-to-source level transformation using the SUIF2 compiler infrastructure. Physical measurements on a high-performance laptop show that total system (i.e., laptop) energy savings of up to 28% can be achieved with performance degradation of less than 5% for the SPECfp95 benchmarks. On average, the system energy and energy-delay product are reduced by 11% and 9%, respectively, with a performance slowdown of 2%. It was also discovered that the energy usage of the programs using our DVS algorithm is within 6% from the theoretical lower bound. To the best of our knowledge, this is one of the first work that evaluates DVS algorithms by physical measurements.

Original languageEnglish (US)
Pages (from-to)38-48
Number of pages11
JournalACM SIGPLAN Notices
Issue number5
StatePublished - May 2003
EventProceedings of the ACM Sigplan 2003 Conference on Programming Language Design and Implementation - San Diego, CA, United States
Duration: Jun 9 2003Jun 11 2003

All Science Journal Classification (ASJC) codes

  • Software
  • Computer Graphics and Computer-Aided Design


  • Dynamic voltage scaling
  • Energy savings

Fingerprint Dive into the research topics of 'The design, implementation, and evaluation of a compiler algorithm for CPU energy reduction'. Together they form a unique fingerprint.

Cite this