TLB Shootdown Mitigation for Low-Power Many-Core Servers with L1 Virtual Caches

Binh Pham, Derek Hower, Abhishek Bhattacharjee, Trey Cain

Research output: Contribution to journalArticle

5 Scopus citations

Abstract

Power efficiency has become one of the most important design constraints for high-performance systems. In this paper, we revisit the design of low-power virtually-addressed caches. While virtually-addressed caches enable significant power savings by obviating the need for Translation Lookaside Buffer (TLB) lookups, they suffer from several challenging design issues that curtail their widespread commercial adoption. We focus on one of these challenges-cache flushes due to virtual page remappings. We use detailed studies on an ARM many-core server to show that this problem degrades performance by up to 25 percent for a mix of multi-programmed and multi-threaded workloads. Interestingly, we observe that many of these flushes are spurious, and caused by an indiscriminate invalidation broadcast on ARM architecture. In response, we propose a low-overhead and readily implementable hardware mechanism using bloom filters to reduce spurious invalidations and mitigate their ill effects.

Original languageEnglish (US)
Pages (from-to)17-20
Number of pages4
JournalIEEE Computer Architecture Letters
Volume17
Issue number1
DOIs
StatePublished - Jan 1 2018

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture

Keywords

  • TLB
  • Virtual Cache
  • multicores
  • multiprogramming
  • multithreading
  • virtual memory

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