Towards a sub-1 V CMOS voltage reference

Laleh Najafizadeh, Igor M. Filanovsky

Research output: Contribution to journalConference articlepeer-review

26 Scopus citations


A sub-1-V CMOS voltage reference, which takes advantage of summing the gate-source voltages of two NMOS transistors operating in saturation region, is presented. Both transistors are working below zero temperature coefficient point and thus the voltage reference is able to operate with low supply voltage. The circuit is implemented in a standard 0.18-μm CMOS process and gives a temperature coefficient of 4 ppm/°C in the range of -50°C to 150°C.

Original languageEnglish (US)
Pages (from-to)I53-I56
JournalProceedings - IEEE International Symposium on Circuits and Systems
StatePublished - 2004
Externally publishedYes
Event2004 IEEE International Symposium on Cirquits and Systems - Proceedings - Vancouver, BC, Canada
Duration: May 23 2004May 26 2004

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering


  • Analog electronics
  • Mobility
  • Temperature effects
  • Threshold voltage
  • Voltage references


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