Using a Jini based desktop grid for test vector compaction and a refined economic model

Tezaswi Raja, Manish Parashar

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Testing of Very Large Scale Integrated(VLSI) circuits is done by designing huge random sets of vectors of which only a few are useful. The process of filtering these good vectors from the overall set is called vector compaction. As the integrated circuits become denser, this problem is becoming a major bottleneck and the computation time could run into days for a single chip. In this paper we demonstrate how a distributed Grid architecture can be used for the speed-up of the problem. The architecture is based on a Jini Desktop Grid. Economic models become a prime issue in such a scenario. The current economic models for minimizing cost or time are ad-hoc and entirely under the control of the broker middle-ware architecture, leaving the end user with little choice. In this paper we present a revised economic model that gives more choice to the user in terms of time and cost before execution. We match the high-level application layer to the available resources by utilizing a system of composite performance modeling of the available resources. We demonstrate the performance of this new architecture on some VLSI benchmark circuits.

Original languageEnglish (US)
Title of host publication2004 IEEE International Symposium on Cluster Computing and the Grid, CCGrid 2004
Pages798-805
Number of pages8
StatePublished - 2004
Event2004 IEEE International Symposium on Cluster Computing and the Grid, CCGrid 2004 - Chicago, IL, United States
Duration: Apr 19 2004Apr 22 2004

Publication series

Name2004 IEEE International Symposium on Cluster Computing and the Grid, CCGrid 2004

Other

Other2004 IEEE International Symposium on Cluster Computing and the Grid, CCGrid 2004
Country/TerritoryUnited States
CityChicago, IL
Period4/19/044/22/04

All Science Journal Classification (ASJC) codes

  • Engineering(all)

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