TY - GEN
T1 - Vertical power JFET in 4H-SiC with an implanted and trenched gate
AU - Zhao, J. H.
AU - Li, X.
AU - Alexandrov, P.
AU - Pan, M.
AU - Weiner, M.
AU - Burke, T.
AU - Khalil, G.
N1 - Publisher Copyright:
© 2001 ISDRS-Univ of Maryland.
PY - 2001
Y1 - 2001
N2 - The most desirable SiC power switches for high temperature applications are SiC JFETs which are non-latch-on and free of gate oxide/insulator voltage-controlled switches. In the vertical form, they can be scaled up to very high current and voltage when implemented in SiC. They also offer the desired negative temperature coefficient for current, and when designed properly, can be made normally-off. Hence, vertical JFETs in SiC have all the desired characteristics of a high power and high temperature SiC switch. In this paper, an implanted-and-trenched gate vertical JFET (IT-JFET) is proposed. Detailed design and modeling results along with device feasibility demonstration are reported. The proposed IT-JFETs are studied by way of two-dimensional numerical simulations by using ISE SiC TCAD Module. The material parameters for 4H-SiC used in the simulations are extracted from the most recently published literatures.
AB - The most desirable SiC power switches for high temperature applications are SiC JFETs which are non-latch-on and free of gate oxide/insulator voltage-controlled switches. In the vertical form, they can be scaled up to very high current and voltage when implemented in SiC. They also offer the desired negative temperature coefficient for current, and when designed properly, can be made normally-off. Hence, vertical JFETs in SiC have all the desired characteristics of a high power and high temperature SiC switch. In this paper, an implanted-and-trenched gate vertical JFET (IT-JFET) is proposed. Detailed design and modeling results along with device feasibility demonstration are reported. The proposed IT-JFETs are studied by way of two-dimensional numerical simulations by using ISE SiC TCAD Module. The material parameters for 4H-SiC used in the simulations are extracted from the most recently published literatures.
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U2 - 10.1109/ISDRS.2001.984484
DO - 10.1109/ISDRS.2001.984484
M3 - Conference contribution
AN - SCOPUS:84961773543
T3 - 2001 International Semiconductor Device Research Symposium, ISDRS 2001 - Proceedings
SP - 235
EP - 238
BT - 2001 International Semiconductor Device Research Symposium, ISDRS 2001 - Proceedings
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - International Semiconductor Device Research Symposium, ISDRS 2001
Y2 - 5 December 2001 through 7 December 2001
ER -