@inproceedings{aef3101d47804b4ca67370e4548d54a1,
title = "VLSI Hardware Architecture for Gaussian Process",
abstract = "Gaussian process (GP) is a popular machine learning technique that is widely used in many application domains, especially in robotics. However, GP is very computation intensive and time consuming during the inference phase, thereby bringing severe challenges for its large-scale deployment in real-time applications. In this paper, we propose two efficient hardware architecture for GP accelerator. One architecture targets for general GP inference, and the other architecture is specifically optimized for the scenario when the data point is gradually observed. Evaluation results show that the proposed hardware accelerator provides significant hardware performance improvement than the general-purpose computing platform.",
keywords = "Gaussian Process, VLSI",
author = "Chunhua Deng and Yongbin Gong and Feng Han and Siyu Liao and Jingang Yi and Bo Yuan",
note = "Publisher Copyright: {\textcopyright} 2020 IEEE.; 54th Asilomar Conference on Signals, Systems and Computers, ACSSC 2020 ; Conference date: 01-11-2020 Through 05-11-2020",
year = "2020",
month = nov,
day = "1",
doi = "10.1109/IEEECONF51394.2020.9443272",
language = "English (US)",
series = "Conference Record - Asilomar Conference on Signals, Systems and Computers",
publisher = "IEEE Computer Society",
pages = "121--124",
editor = "Matthews, {Michael B.}",
booktitle = "Conference Record of the 54th Asilomar Conference on Signals, Systems and Computers, ACSSC 2020",
address = "United States",
}