In this paper we highlight the complementarities of process-induced stress and wafer level stress (sSOI). We first present a state of the art of the various strain engineering techniques used in production for both PMOS and NMOS devices and discuss their scalability for 45nm and 32 nm nodes using some mechanical modeling. In a second part, we explain how wafer level stress can be used together with process-induced stress to overcome these difficulties and insure further performance enhancement. We discuss some device data showing compatibility and additivity of process-induced and wafer level stress. Finally, we give an overview of further sSOI developments that will insure scalability beyond 32nm. copyright The Electrochemical Society.
|Original language||English (US)|
|Number of pages||12|
|State||Published - Dec 1 2006|
|Event||SiGe and Ge: Materials, Processing, and Devices - 210th Electrochemical Society Meeting - Cancun, Mexico|
Duration: Oct 29 2006 → Nov 3 2006
All Science Journal Classification (ASJC) codes