Wafer-level stress in combination with process induced stress for optimum performance enhancement

I. Cayrefourcq, A. Boussagol, G. Celler

Research output: Contribution to journalConference article

11 Citations (Scopus)

Abstract

In this paper we highlight the complementarities of process-induced stress and wafer level stress (sSOI). We first present a state of the art of the various strain engineering techniques used in production for both PMOS and NMOS devices and discuss their scalability for 45nm and 32 nm nodes using some mechanical modeling. In a second part, we explain how wafer level stress can be used together with process-induced stress to overcome these difficulties and insure further performance enhancement. We discuss some device data showing compatibility and additivity of process-induced and wafer level stress. Finally, we give an overview of further sSOI developments that will insure scalability beyond 32nm. copyright The Electrochemical Society.

Original languageEnglish (US)
Pages (from-to)399-410
Number of pages12
JournalECS Transactions
Volume3
Issue number7
DOIs
StatePublished - Dec 1 2006
Externally publishedYes
EventSiGe and Ge: Materials, Processing, and Devices - 210th Electrochemical Society Meeting - Cancun, Mexico
Duration: Oct 29 2006Nov 3 2006

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Scalability

All Science Journal Classification (ASJC) codes

  • Engineering(all)

Cite this

@article{85f7bb6058274847a02bb74dfc66a892,
title = "Wafer-level stress in combination with process induced stress for optimum performance enhancement",
abstract = "In this paper we highlight the complementarities of process-induced stress and wafer level stress (sSOI). We first present a state of the art of the various strain engineering techniques used in production for both PMOS and NMOS devices and discuss their scalability for 45nm and 32 nm nodes using some mechanical modeling. In a second part, we explain how wafer level stress can be used together with process-induced stress to overcome these difficulties and insure further performance enhancement. We discuss some device data showing compatibility and additivity of process-induced and wafer level stress. Finally, we give an overview of further sSOI developments that will insure scalability beyond 32nm. copyright The Electrochemical Society.",
author = "I. Cayrefourcq and A. Boussagol and G. Celler",
year = "2006",
month = "12",
day = "1",
doi = "10.1149/1.2355837",
language = "English (US)",
volume = "3",
pages = "399--410",
journal = "ECS Transactions",
issn = "1938-5862",
publisher = "Electrochemical Society, Inc.",
number = "7",

}

Wafer-level stress in combination with process induced stress for optimum performance enhancement. / Cayrefourcq, I.; Boussagol, A.; Celler, G.

In: ECS Transactions, Vol. 3, No. 7, 01.12.2006, p. 399-410.

Research output: Contribution to journalConference article

TY - JOUR

T1 - Wafer-level stress in combination with process induced stress for optimum performance enhancement

AU - Cayrefourcq, I.

AU - Boussagol, A.

AU - Celler, G.

PY - 2006/12/1

Y1 - 2006/12/1

N2 - In this paper we highlight the complementarities of process-induced stress and wafer level stress (sSOI). We first present a state of the art of the various strain engineering techniques used in production for both PMOS and NMOS devices and discuss their scalability for 45nm and 32 nm nodes using some mechanical modeling. In a second part, we explain how wafer level stress can be used together with process-induced stress to overcome these difficulties and insure further performance enhancement. We discuss some device data showing compatibility and additivity of process-induced and wafer level stress. Finally, we give an overview of further sSOI developments that will insure scalability beyond 32nm. copyright The Electrochemical Society.

AB - In this paper we highlight the complementarities of process-induced stress and wafer level stress (sSOI). We first present a state of the art of the various strain engineering techniques used in production for both PMOS and NMOS devices and discuss their scalability for 45nm and 32 nm nodes using some mechanical modeling. In a second part, we explain how wafer level stress can be used together with process-induced stress to overcome these difficulties and insure further performance enhancement. We discuss some device data showing compatibility and additivity of process-induced and wafer level stress. Finally, we give an overview of further sSOI developments that will insure scalability beyond 32nm. copyright The Electrochemical Society.

UR - http://www.scopus.com/inward/record.url?scp=33846960203&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=33846960203&partnerID=8YFLogxK

U2 - 10.1149/1.2355837

DO - 10.1149/1.2355837

M3 - Conference article

AN - SCOPUS:33846960203

VL - 3

SP - 399

EP - 410

JO - ECS Transactions

JF - ECS Transactions

SN - 1938-5862

IS - 7

ER -